On-chip Electrostatic Discharge (ESD) design in advanced submicron complementary metal-oxide-semiconductor (CMOS) processes becomes more challenging when process feature size continues to scale down. Shallower junctions, thicker salicides, and thinner epitaxial layers in advanced CMOS processes have shown negative impact of the ESD capability of a process. Developing a built-in ESD robustness process or using an extra implant to make the junction deeper are approaches to improve process ESD capability thus improve product ESD protection level. However, for a given process technology, product ESD protection performance will totally rely on the implemented ESD protection scheme and methodology.
In advanced submicron CMOS processes, the thin gate oxide and low drain/substrate breakdown voltage make n-channel metal-oxide-semiconductor (NMOS) the most vulnerable device to an ESD event. Using additional process steps to block the salicide in the ESD NMOS and output NMOS could achieve an adequate ESD performance. However, this method increases product costs due to additional process masks required. Additionally, extra impedance is added into the signal path due to the non-silicided contact-to-gate spacing (CGS) of the output NMOS. The additional impedance in the signal path limits its current driving capability and its application in high speed analog/mixed-signal designs. The gate-coupled NMOS (GCNMOS) was first proposed as an effective protection device for CMOS. Subsequently, a substrate trigger NMOS (STNMOS) protection scheme for advanced submicron CMOS processes has been developed which does not require the use of additional masks or introduction of additional impedance. The requirement of a large chip capacitance on the power supplies in this protection scheme also limits its application in small analog/mixed-signal chip designs.
A key issue for ESD design is to ensure the ESD protection circuit turns on with a small on-resistance so as to conduct most of the ESD current during an ESD event. A trigger element with a low trigger voltage is required for such an ESD protection scheme. In advanced submicron BiCMOS processes, a zener breakdown voltage of about a base-emitter junction of a bipolar junction transistor (BJT) is utilized for that purpose. In advanced submicron CMOS processes, this option is not available. The lowest junction breakdown voltage is known as the NMOS drain junction breakdown voltage. Therefore, the characteristics of an NMOS device in a particular process dictate the ESD protection design.
FIG. 1a illustrates graphs of current (I) (in milliamps) vs. voltage (in volts, V) of a typical I-V breakdown characteristic for a NMOS transistor under different gate bias conditions as measured in a TLP system with a 200 ns pulse width. Vt1 is the first turn-on voltage of a parasitic lateral npn (LNPN) transistor associated with the NMOS transistor. Vt2 is the second breakdown voltage and Vsp is the snapback voltage. Beyond the second breakdown which is signified by Vt2, the NMOS enters the regime of thermal runaway which can result in damage to the NMOS. The corresponding second breakdown current (It2), which is not labeled in FIG. 1a, but which is the corresponding current for Vt2 on the I-V characteristic shown in FIG. 1a, is a key process ESD parameter for monitoring the high current handling capability of the NMOS. When the NMOS operates in the snapback mode or the bipolar breakdown region, the lateral NPN (LNPN) of the NMOS conducts most of the drain terminal current. It has been found that It2 strongly depends on the Beta of the LNPN, the NMOS channel length, the salicide thickness, the drain junction depth, and the epi layer thickness. An improved It2 can result from an optimized process. For a given process, the success of a typical multi-finger NMOS protection design strictly depends on how to design a protection circuit to enable most of the LNPNs, which are the NMOS fingers of a protection NMOS scheme, to turn on and uniformly conduct ESD current during ESD events. Uniformity in turning on the LNPNs (or NMOS fingers) can be achieved by increasing snapback on-resistance (Ron) to increase Vt2 to being greater than Vt1 or by reducing Vt1 to being less than Vt2. If Vt1 is designed to be lower than Vt2, each LNPN of a NMOS finger would, during an ESD event, turn on to conduct the ESD current before any single LNPN reaches second breakdown, Vt2.
FIG. 2a illustrates a simplified layout of the fingered NMOS showing the fingers embodied in the alternating pattern of drains (D) and sources (S). FIG. 2b illustrates a layout/schematic of the fingered NMOS.
On-resistance, Ron, can be easily increased by increasing the drain/source contact to poly gate spacing in nonsilicided processes. But in silicided processes, a silicide block mask is needed in order to get a good ESD protection performance. Increasing substrate potential or applying a small positive bias voltage to the substrate can reduce Vt1 below Vt2. With this technique, a Substrate Triggering NMOS (STNMOS) protection scheme was recently developed for silicide submicron CMOS processes. This type of ESD protection scheme works with large digital application-specific processor (ASPs) chips. However, the large chip capacitance associated with the relatively large size of these ASP chips limits the application of the STNMOS for a small mixed-signal chip. The reduction of Vt1 can also be achieved by increasing the NMOS gate potential. As shown in FIG. 1a, when the gate voltage is high enough, Vt1 is approximately Vsp which is less than Vt2.